#ifndef __LS220_H #define __LS220_H // -- for field lock use -- #define CHANGE_MPGVID_CONTROL #define CHANGE_REG274 #define DO_NOT_TOUCH_REG324 #define LS240 // #define WINDOWS2000 // for Windows 2000 #ifndef LS240 #define DRAM_BASE 0x200000L #else #define DRAM_BASE 0x400000L #endif #define PAL_MAP #ifdef PAL_MAP #define VID_FIFO_OFF 0x1a3000L #define VID_FIFO_LEN 0x3e000L #define PTS_FIFO_OFF 0x1a2800L #define PTS_FIFO_LEN 0x800L #define SUB_FIFO_OFF 0x1e2000L #define OSD_FIFO_OFF 0x1e1000L #define OSD_FIFO_LEN 0x1000L #else #define VID_FIFO_OFF 0x1c8000L #define VID_FIFO_LEN 0x20000L #define PTS_FIFO_OFF 0x1c7a00L #define PTS_FIFO_LEN 0x600L #endif #define LS220_VID_FIFO (DRAM_BASE+VID_FIFO_OFF) #define DSPMEM_BASE (DRAM_BASE+0x1f0000L) #define DSPPROG_BASE (DSPMEM_BASE-DRAM_BASE) #define DSPPROG_OFF 0x1800L #define DSPPROG_SIZE 0x6000L #define AUD_FIFO_LEN 0x2000L #define AUD_FIFO_OFF 0x1fc000L #define AUD_PTS_LEN 0x400L #define AUD_PTS_OFF 0x1ffa00L // Subpict definition #define FIFO_SIZE 8 // PTS FIFO entry count #define HIGH_FIFO 32 // HighLight Fifo size #define SCRM_FIFO 0x800 // Scramble buffer size #define SPBLOCK ( 0xE000 - HIGH_FIFO - SCRM_FIFO ) // 56K - 32 bytes - 2k #define SubBLOCK 0xE00 // PTS + DCI = 3.5K #define DCIBLOCK ( SubBLOCK - 8*FIFO_SIZE ) #define PxdBLOCK ( SPBLOCK - SubBLOCK ) #define FStart 0x20 // PTS FIFO Start Address #define SUBBASE ( DRAM_BASE + SUB_FIFO_OFF ) #define LS220_DSP_REG 0x100L #define LS220_MPG_REG 0x180L #define LS220_SYNC_REG 0x200L #define LS220_PCM_REG 0x280L #define LS220_VID_REG 0x300L // SYNC REGS #define SYNC_AUD_CONTROL (LS220_SYNC_REG+0x00) #define SYNC_VID_CONTROL (LS220_SYNC_REG+0x04) #define SYNC_WAIT_LINE (LS220_SYNC_REG+0x0c) #define SYNC_FRAME_PERIOD (LS220_SYNC_REG+0x10) #define SYNC_STC (LS220_SYNC_REG+0x18) #define PTS_FIFO_START (LS220_SYNC_REG+0x20) #define PTS_FIFO_END (LS220_SYNC_REG+0x24) #define PTS_FIFO_WRITE (LS220_SYNC_REG+0x28) #define PTS_FIFO_READ (LS220_SYNC_REG+0x2c) #define SYNC_VIDEO_PTS (LS220_SYNC_REG+0x50) #define SYNC_INT_CTRL (LS220_SYNC_REG+0x74) #define SYNC_INT_FORCE (LS220_SYNC_REG+0x78) // MPEG VIDEO REGS #define MPGVID_CONTROL (LS220_MPG_REG+0x0) #define MPGVID_SETUP (LS220_MPG_REG+0x4) #define MPGVID_FIFO_START (LS220_MPG_REG+0x8) #define MPGVID_FIFO_END (LS220_MPG_REG+0xc) #define MPGVID_FIFO_POS (LS220_MPG_REG+0x10) #define MPGVID_FIFO_FORCE (LS220_MPG_REG+0x14) #define MPGVID_FIFO_ADDBLOCK (LS220_MPG_REG+0x18) #define MPGVID_FIFO_BYTES (LS220_MPG_REG+0x1c) #define MPGVID_FIFO_INTLEVEL (LS220_MPG_REG+0x20) #define MPGVID_TOTAL_BYTES (LS220_MPG_REG+0x24) #define MPGVID_ERROR (LS220_MPG_REG+0x28) #define MPGVID_MB_WIDTH (LS220_MPG_REG+0x2c) #define MPGVID_MB_HEIGHT (LS220_MPG_REG+0x30) #define MPGVID_DEBUG1 (LS220_MPG_REG+0x38) #define MPGVID_DEBUG2 (LS220_MPG_REG+0x3c) //VID_REG #define VIDP_GPIO (LS220_VID_REG+0x50) // PCM REG #define PCM_FREQ_CONTROL (LS220_PCM_REG+0x0) #define PCM_OUTPUT_CONTROL (LS220_PCM_REG+0x4) #define PCM_FIFO_START (LS220_PCM_REG+0x8) #define PCM_FIFO_END (LS220_PCM_REG+0xc) // DSP REGS #define DSP_CODE_ADDR (LS220_DSP_REG+0x0) // DSP INTERAL MEMORY #define DSPMEM_DRV_RET (DSPMEM_BASE+0xfef0L) #define DSPMEM_ACC (DSPMEM_BASE+0xfef5L) #define DSPMEM_ACC4 (DSPMEM_BASE+0xfef4L) #define DSPMEM_CHAL_KEY (DSPMEM_BASE+0xfef6L) #define DSPMEM_LOCK (DSPMEM_BASE+0xff78L) // #define DSPMEM_UCLOCK (DSPMEM_BASE+0xff78L) // delete by nick #define DSPMEM_AUDIO_CONF (DSPMEM_BASE+0xff7cL) // #define DSPMEM_SPDIF (DSPMEM_BASE+0xff7cL) // delete by nick #define DSPMEM_AC3_CONF (DSPMEM_BASE+0xff80L) #define DSPMEM_KARAOKE (DSPMEM_BASE+0xff8c) // KARAOKE property #define DSPMEM_INT_MASK (DSPMEM_BASE+0xffa4L) #define DSPMEM_INT_STATUS (DSPMEM_BASE+0xffa8L) #define DSPMEM_INT_THREHOLD (DSPMEM_BASE+0xffacL) #define DSPMEM_VOLUME_LEVEL (DSPMEM_BASE+0xffb0L) #define DSPMEM_PTS_START (DSPMEM_BASE+0xffd0L) #define DSPMEM_PTS_END (DSPMEM_BASE+0xffd4L) #define DSPMEM_PTS_WR (DSPMEM_BASE+0xffd8L) #define DSPMEM_PTS_RD (DSPMEM_BASE+0xffdcL) #define DSPMEM_FIFO_START (DSPMEM_BASE+0xffe0L) #define DSPMEM_FIFO_END (DSPMEM_BASE+0xffe4L) #define DSPMEM_FIFO_WR (DSPMEM_BASE+0xffe8L) #define DSPMEM_FIFO_RD (DSPMEM_BASE+0xffecL) #define DSPMEM_CMD (DSPMEM_BASE+0xfff0L) #define DSPMEM_STATUS (DSPMEM_BASE+0xfff8L) #define DSP_CMD_NOP 0x00 #define DSP_CMD_AC3 0x80 #define DSP_CMD_MPEG1 0x81 #define DSP_CMD_MPEG2 0x82 #define DSP_CMD_PCM 0x83 #define DSP_CMD_PLAY 0x84 #define DSP_CMD_STOPF 0x85 #define DSP_CMD_PAUSE 0x86 #define DSP_CMD_MUTE 0x87 #define DSP_CMD_UNMUTE 0x88 #define DSP_CMD_CONFIG 0x89 #define DSP_CMD_VER 0x8a #define DSP_CMD_STATUS 0x8b #define DSP_CMD_VOLUME 0x8c #define DSP_CMD_INITDONE 0x8d #define DSP_CMD_FRAME 0xa0 #define DSP_CMD_CLRAUTH 0xa1 #define DSP_CMD_DECAUTH 0xa2 #define DSP_CMD_DRVAUTH 0xa3 #define DSP_CMD_KEYSHARE 0xa4 #define DSP_CMD_DISCKEY 0xa5 #define DSP_CMD_TITLEKEY 0xa6 #endif